DS92LV2421_16 Datasheet, PDF (24/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Feature Description (continued)
7.3.2 Video Control Signal Filter – Serializer and Deserializer
When operating the devices in normal mode, the video control signals (DE, HS, VS) have the following
restrictions:
• Normal mode with control signal filter enabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 CLK
cycles or longer.
• Normal mode with control signal filter disabled:
– DE and HS: Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS: Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video control signals are defined as low frequency signals with limited transitions. Glitches of a control signal can
cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise
on the control signals (see Figure 24).
CLKIN
HS/VS/DE
IN
Latency
CLKOUT
HS/VS/DE Pulses 1 or 2
OUT CLK cycles wide
Filtered OUT
Figure 24. Video Control Signal Filter Waveform
7.3.3 Serializer Functional Description
The serializer converts a wide parallel input bus to a single serial output data stream and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured through external pins or
through the optional serial control bus. The serializer features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning, and Channel Link II data coding that
provides randomization, scrambling, and DC balancing of the data. The serializer includes multiple features to
reduce EMI associated with display data transmission. This includes the randomization and scrambling of the
data and system spread spectrum clock support. The serializer features power-saving features with a sleep
mode, auto stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility (see also Optional Serial
Bus Control and Built-In Self Test (BIST)).
7.3.3.1 EMI Reduction Features
7.3.3.1.1 Data Randomization and Scrambling
Channel Link II serializers and deserializers feature a three-step encoding process that enables the use of AC-
coupled interconnects and also helps to manage EMI. The serializer first passes the parallel data through a
scrambler which randomizes the data. The randomized data is then DC-balanced. The DC-balanced and
randomized data then goes through a bit-shuffling circuit and is transmitted out on the serial line. This encoding
process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial
stream ranges from the parallel clock frequency to the serial Nyquist rate. For example, if the serializer and
deserializer chip set is operating at a parallel clock frequency of 75 MHz, the resulting frequency content of serial
stream ranges from 75 MHz to 1.05 GHz (75 MHz × 28 bits / 2 = 2.1 GHz / 2 = 1.05 GHz).
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