DS92LV2421_16 Datasheet, PDF (48/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Layout Guidelines (continued)
Table 20. No Pullback LLP Stencil Aperture Summary for DS92LV2421 and DS92LV2422
DEVICE
PIN
COUNT
DS92LV2421
48
DS92LV2422
60
MKT
DWG
PCB I/O
PAD SIZE
(mm)
SQA48A 0.25 × 0.6
SQA60B 0.25 × 0.8
PCB
PITCH
(mm)
0.5
0.5
PCB DAP
SIZE (mm)
5.1 × 5.1
7.2 × 7.2
STENCIL I/O
APERTURE
(mm)
0.25 × 0.7
0.25 × 0.9
STENCIL DAP
APERTURE
(mm)
1.1 × 1.1
1.16 × 1.16
NUMBER OF
DAP
APERTURE
OPENINGS
16
25
GAP BETWEEN
DAP APERTURE
(Dim A mm)
0.2
0.3
Figure 44. 48-Pin WQFN Stencil Example of Via and Opening Placement
Information on the WQFN style package is provided in Leadless Leadframe Package (LLP) Application Report
(SNOA401).
10.1.2 Transmission Media
The serializer and deserializer chipset is intended to be used in a point-to-point configuration through a PCB
trace or through twisted pair cable. The serializer and deserializer provide internal terminations for a clean
signaling environment. The interconnect for CML must present a differential impedance of 100 Ω. Use cables and
connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-
shielded cables may be used depending upon the noise environment and application requirements.
10.1.3 LVDS Interconnect Guidelines
See AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) and AN-905 Transmission
Line RAPIDESIGNER Operation and Applications Guide (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S, 2S, 3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
48
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