DS92LV2421_16 Datasheet, PDF (33/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
7.3.4.8 Deserializer Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by register.
7.3.4.9 Deserializer Map Select
This feature may be controlled by the external pin or by register.
MAP_SEL1
L
L
H
Table 10. Map Select Configuration
INPUTS
MAP_SEL0
L
H
H or L
EFFECT
Bit 4, Bit 5 on LSB
DEFAULT
LSB 0 or 1
LSB 0
7.3.4.10 Deserializer Strap Input Pins
Configuration of the device may be done through configuration input pins and the strap input pins, or through the
serial control bus. The strap input pins share select parallel bus output pins. They are used to load in
configuration values during the initial power-up sequence of the device. Only a pullup on the pin is required when
a high is desired. By default, the pad has an internal pulldown and bias low by itself. The recommended value of
the pullup is 10 kΩ to V_DDIO; open (NC) for low, because no pulldown is required (internal pulldown). If using the
serial control bus, no pullups are required.
7.3.4.11 Optional Serial Bus Control
See Optional Serial Bus Control.
7.3.4.12 Optional BIST Mode
See Built-In Self Test (BIST).
7.3.5 Built-In Self Test (BIST)
An optional At-Speed Built-In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test, and for system diagnostics. In BIST mode,
only an input clock is required along with control to the serializer and deserializer BISTEN input pins. The
serializer outputs a test pattern (PRBS-7) and drives the link at speed. The deserializer detects the PRBS-7
pattern and monitors it for errors. A PASS output pin toggles to flag any payloads that are received with 1 to 24
errors. Upon completion of the test, the result of the test is held on the PASS output until reset (new BIST test or
power down). A high on PASS indicates NO ERRORS were detected. A low on PASS indicates one or more
errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN
pin. During the BIST duration, the deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1, 2,
3). See Sample BIST Sequence for entering BIST mode and control.
7.3.5.1 Sample BIST Sequence
See Figure 32 for the BIST mode flow diagram.
Step 1: Place the DS92LV2421 serializer in BIST Mode by setting serializer BISTEN = H. For the DS92LV2421
serializer or DS99R421-Q1 FPD-Link II serializer, BIST Mode is enabled through the BISTEN pin. For the
DS90C241 serializer or DS90UR241 serializer, BIST mode is entered by setting all the input data of the device to
a low state. A CLKIN is required for BIST. When the deserializer detects the BIST mode pattern and command
(DCA and DCB code), the data and control signal outputs are shut off.
Step 2: Place the DS92LV2422 deserializer in BIST mode by setting BISTEN = H. The deserializer is now in
BIST mode and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected,
the PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
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