DS92LV2421_16 Datasheet, PDF (11/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
6.4 Thermal Information
Over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC⁽¹⁾
DS92LV2421
RHS (WQFN)
DS92LV2422
NKB (WQFN)
UNIT
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
48 PINS
30.3
11.5
7.3
0.1
7.3
2.7
60 PINS
26.9
9.1
6
0.1
6
1.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Based on nine thermal vias.
6.5 Electrical Characteristics – Serializer DC
Over recommended operating supply and temperature ranges (unless otherwise noted).^(1)(2)(3)
PARAMETER
TEST CONDITIONS
MIN
LVCMOS INPUT DC SPECIFICATIONS
V_IH
High level input voltage
V_DDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,
VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)
V_DDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,
VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)
2.2
0.65 × V_DDIO
V_IL
Low level input voltage
V_DDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,
VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)
V_DDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB,
VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)
GND
GND
I_IN
Input current
V_IN = 0 V or V_DDIO (DI[23:0],
V_DDIO = 3 V to 3.6 V
–15
CI1,CI2,CI3, CLKIN, PDB, VODSEL,
RFB, BISTEN, and CONFIG[1:0] pins) ^VDDIO ^{= 1.7 V to 1.89 V}
–15
CML DRIVER DC SPECIFICATIONS
R_L = 100 Ω, de-emphasis = disabled VODSEL = 0
V_OD
Differential output voltage
(see Figure 2; DOUT+ and DOUT–
pins)
VODSEL = 1
±205
±320
VOD_p-p
Differential output voltage
(DOUT+) – (DOUT-)
R_L = 100 Ω, de-emphasis = disabled
(see Figure 2; DOUT+ and DOUT–
pins)
VODSEL = 0
VODSEL = 1
ΔV_OD Output voltage unbalance
R_L = 100 Ω, de-emphasis = disabled, VODSEL = L (DOUT+ and
DOUT– pins)
V_OS
Offset voltage
(single-ended)
At TP A and B (see Figure 1), R_L =
100 Ω, de-emphasis = disabled
(DOUT+ and DOUT– pins)
VODSEL = 0
VODSEL = 1
ΔV_OS
Offset voltage unbalance
(single-ended)
At TP A and B (see Figure 1), R_L = 100 Ω,
de-emphasis = disabled (DOUT+ and DOUT– pins)
I_OS
Output short circuit current
DOUT± = 0 V, de-emphasis = disabled,
VODSEL = 0 (DOUT+ and DOUT– pins)
R_TO
Internal output termination
resistor
DOUT+ and DOUT– pins
80
TYP
±1
±1
±280
±420
560
840
1
1.65
1.575
1
–36
100
MAX
V_DDIO
V_DDIO
0.8
0.35 × V_DDIO
15
15
±355
±520
50
120
UNIT
V
V
μA
mV
mV_p-p
mV
V
mV
mA
Ω
(1) The electrical characteristics tables list verified specifications under the listed recommended operating conditions except as otherwise
modified or specified by the electrical characteristics conditions or notes. Typical specifications are estimations only and are not verified.
(2) Typical values represent most likely parametric norms at V_DD = 3.3 V, T_A = 25°C, and at the recommended operation conditions at the
time of product characterization and are not verified.
(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except V_OD, ΔV_OD, V_TH, and V_TL, which are differential voltages.
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