DS92LV2411_15 Datasheet, PDF (9/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Pin Functions, DS92LV2412 Deserializer ⁽¹⁾ (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
CHANNEL-LINK II — CML SERIAL INTERFACE
CMF
51
I, Analog Common-Mode Filter
VCM center-tap is a virtual ground which may be AC coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
RIN+
49
I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor.
RIN-
50
I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
ROUT+
52
O, CML True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT-
53
POWER AND GROUND⁽³⁾
O, CML
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
GND
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
VDDCMLO
54
Power RX High Speed Logic Power, 1.8 V ± 5%
VDDIO
VDDIR
13, 24, 38
48
Power
Power
LVCMOS I/O Power, 1.8 V ± 5% OR 3.3 V ± 10% (V_DDIO)
Input Power, 1.8 V ±5%
VDDL
29
Power Logic Power, 1.8 V ±5%
VDDPR
57
Power PLL Power, 1.8 V ±5%
VDDR
43, 55
Power RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power SSCG Power, 1.8 V ±5%
(3) Power must be supplied to all power Pins for normal operation
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