DS92LV2411_15 Datasheet, PDF (1/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
DS92LV241x 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer
1 Features
•1 24-Bit Data, 3–Bit Control, 5 to 50 MHz Clock
• Application Payloads up to 1.2 Gbps
• AC Coupled Interconnects: STP up to 10 m or
Coax 20+ m
• 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
• Integrated Terminations on Ser and Des
• AT-SPEED BIST Mode and Reporting Pin
• Configurable by Pins or I2C Compatible Serial
Control Bus
• Power Down Mode Minimizes Power Dissipation
• >8 kV HBM ESD Rating
• SERIALIZER — DS92LV2411
– Supports Spread Spectrum Clocking (SSC) on
Inputs
– Data Scrambler for Reduced EMI
– DC-Balance Encoder for AC Coupling
– Selectable Output V_OD and Adjustable De-
emphasis
• DESERIALIZER — DS92LV2412
– Random Data Lock; no Reference Clock
Required
– Adjustable Input Receiver Equalization
– LOCK (Real Time Link Status) Reporting Pin
– Selectable Spread Spectrum Clock Generation
(SSCG) and Output Slew Rate Control (OS) to
Reduce EMI
2 Applications
• Embedded Video and Display
• Medical Imaging
• Factory Automation
• Office Automation — Printer, Scanner
• Security and Video Surveillance
• General Purpose Data Communication
3 Description
The DS92LV2411 (Serializer) and DS92LV2412
(Deserializer) chipset translates a parallel 24–bit
LVCMOS data interface into a single high-speed CML
serial interface with embedded clock information. This
single serial stream eliminates skew issues between
clock and data, reduces connector size and
interconnect cost for transferring a 24-bit, or less, bus
over FR-4 printed circuit board backplanes,
differential or coax cables.
In addition to the 24-bit data bus interface, the
DS92LV2411/12 also features a 3-bit control bus for
slow speed signals. This allows implementing video
and display applications with up to 24–bits per pixel
(RGB888).
Programmable transmit de-emphasis, receive
equalization, on-chip scrambling and DC balancing
enables long distance transmission over lossy cables
and backplanes. The DS92LV2412 automatically
locks to incoming data without an external reference
clock or special sync patterns, providing easy “plug-
and-go” or “hot plug” operation. EMI is minimized by
the use of low voltage differential signaling, receiver
drive strength control, and spread spectrum clocking
capability.
The DS92LV2411/12 chipset is programmable though
an I2C interface as well as through Pins. A built-in
AT-SPEED BIST feature validates link integrity and
may be used for system diagnostics.
The DS92LV2411 is offered in a 48-Pin WQFN and
the DS92LV2412 is offered in a 60-Pin WQFN
package. Both devices operate over the full industrial
temperature range of -40°C to +85°C.
Device Information
PART NUMBER
PACKAGE BODY SIZE (NOM)
DS92LV2411
WQFN (48) 7.00 mm × 7.00 mm
DS92LV2412
WQFN (60) 9.00 mm × 9.00 mm
4 Typical Application Schematic
VDDIO VDDn
(1.8V or 3.3V) 1.8V
VDDn VDDIO
1.8V (1.8V or 3.3V)
Graphic
Processor
OR
Video
Imager
OR
ASIC/FPGA
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
CLKIN
PDB
BISTEN
Optional
SCL
SDA
ID[x]
DOUT+
DOUT-
DS92LV2411
Serializer
DAP
Channel Link II
1 Pair /AC Coupled
0.1 2F
0.1 2F
100 ohm STP Cable
CMF
RFB
VODSEL
DeEmph
Optional
PDB
BISTEN
SCL
SDA
ID[x]
RIN+
RIN-
DS92LV2412
Deserializer
DAP
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
CLKOUT
LOCK
PASS
STRAP pins
not shown
24-bit RGB
Display
OR
ASIC/FPGA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.