DS92LV2411_15 Datasheet, PDF (4/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
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Pin Functions, DS92LV2411 Serializer⁽¹⁾ (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
CLKIN
10
I, LVCMOS Clock Input
w/ pull-down Latch/data strobe edge set by RFB Pin.
DI[7:0]
34, 33, 32, 29, I, LVCMOS Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull-down For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
DI[15:8]
42, 41, 40, 39, I, LVCMOS Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull-down For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
DI[23:16]
2, 1, 48, 47, I, LVCMOS Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull-down For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
CONTROL AND CONFIGURATION
BISTEN
31
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
CONFIG[1:
0]
13, 12
I, LVCMOS
w/ pull-down
00: Control Signal Filter DISABLED. Interfaces with DS92LV2412 or DS92LV0412
01: Control Signal Filter ENABLED. Interfaces with DS92LV2412 or DS92LV0412
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
De-Emph
23
I, Analog De-Emphasis Control
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this Pin to GND or control via register.
See Table 2.
This can also be controlled by I2C register access.
ID[x]
6
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
PDB
21
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
RES[2:0]
18, 16, 15
I, LVCMOS Reserved - tie LOW
w/ pull-down
RFB
11
I, LVCMOS Clock Input Latch/Data Strobe Edge Select
w/ pull-down RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
This can also be controlled by I2C register access.
SCL
8
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
SDA
9
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor 3.3V.
VODSEL
24
I, LVCMOS Differential Driver Output Voltage Select
w/ pull-down VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications
VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
This is can also be control by I2C register.
4
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