DS92LV2411_15 Datasheet, PDF (20/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
7.11 Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
t_RCP
CLK Output Period
t_RCP = t_TCP
CLKOUT
t_RDC
CLK Output Duty Cycle SSCG = OFF, 5 – 50MHz
SSCG = ON, 5 – 20 MHz
20
0.43T
0.35T
SSCG = ON, 20 – 50 MHz
0.40T
t_CLH
LVCMOS
Low-to-High
Transition Time,
Figure 10
V_DDIO = 1.8V,
C_L = 4pF,
OS_CLKOUT/DATA = L
V_DDIO = 3.3V
C_L = 4pF,
OS_CLKOUT/DATA = H
CLKOUT/DO[23:0],
CO1, CO2, CO3
t_CHL
LVCMOS
High-to-Low
Transition Time,
Figure 10
V_DDIO = 1.8V
C_L = 4pF,
OS_CLKOUT/DATA = L
V_DDIO = 3.3V
C_L = 8 pF,
OS_CLKOUT/DATA = H
CLKOUT/DO[23:0],
CO1, CO2, CO3
t_ROS
t_ROH
t_DDLT
Data Valid before
CLKOUT – Set Up Time,
Figure 14
Data Valid after
CLKOUT – Hold Time,
Figure 14
Deserializer Lock Time,
Figure 13
V_DDIO = 1.71 to 1.89V or
V_DDIO = 3.0 to 3.6V
C_L = 4pF (lumped load)
V_DDIO = 1.71 to 1.89V or
V_DDIO = 3.0 to 3.6V
C_L = 4pF (lumped load)
SSC[3:0] = OFF,
See ⁽¹⁾
DO[23:0], CO1, CO2,
CO3
DO[23:0], CO1, CO2,
CO3
CLKOUT = 5MHz
0.27
0.4
SSC[3:0] = OFF,
See ⁽¹⁾
CLKOUT = 50MHz
SSC[3:0] = ON,
See ⁽¹⁾
CLKOUT = 5MHz
SSC[3:0] = ON,
See ⁽¹⁾
CLKOUT = 50MHz
t_DD
Des Delay - Latency,
SSC[3:0] = ON,
Figure 11
See ⁽²⁾
CLKOUT = 5 to 50 MHz
t_DPJ
Des Period Jitter
SSC[3:0] = OFF,
See ⁽³⁾
CLKOUT = 5MHz
CLKOUT = 10MHz
CLKOUT = 50MHz
t_DCCJ
Des Cycle-to-Cycle Jitter SSC[3:0] = OFF,
See ⁽²⁾
CLKOUT = 5MHz
CLKOUT = 10MHz
CLKOUT = 50MHz
t_IIT
Des Input Jitter
EQ = OFF,
jitter freq <2MHz
Tolerance, Figure 16
SSCG = OFF,
CLKOUT = 50 MHz
jitter freq >6MHz
BIST MODE
t_PASS
BIST PASS Valid Time,
BISTEN = 1, Figure 17
SSCG MODE
f_DEV
Spread Spectrum
Clocking Deviation
Frequency
Under typical conditions
CLKOUT = 5 to 50 MHz,
SSC[3:0] = ON
±0.005
f_MOD
f_MOD
Spread Spectrum
Under typical conditions CLKOUT = 5 to 50 MHz,
Clocking Modulation
SSC[3:0] = ON
8
Frequency
TYP
T
0.50T
0.59T
0.53T
2.1
2.0
1.6
1.5
0.45
0.55
3
4
30
6
139*T
975
500
550
675
375
500
0.9
0.5
1
MAX
200
0.57T
0.65T
0.60T
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
T
T
ms
ms
ms
ms
140*T ns
1700
1000
1250
1150
900
1150
ps
ps
ps
ps
ps
ps
UI ⁽⁴⁾
UI ⁽⁴⁾
10 µs
±0.02
f_MOD
KHz
100 kHz
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock.
(2) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
(3) t_DPJ is the maximum amount the period is allowed to deviate over many samples.
(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / (28*CLK) ). The UI scales with clock frequency.
20
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