DS92LV2411_15 Datasheet, PDF (25/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
8.3.1.3 Power Saving Features
8.3.1.3.1 Ser — Power Down Feature (PDB)
The Ser has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin is controlled by the host and is
used to save power, disabling the link when the it is not needed. In the POWER DOWN mode, the high-speed
driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN, the optional Serial
Bus Control Registers are RESET.
8.3.1.3.2 Ser — Stop Clock Feature
The Ser will enter a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when the
input clock frequency is less than 3 MHz. The clock should be held at a static Low or high state. When the
CLKIN starts again, the Ser will then lock to the valid input clock and then transmits the serial data to the Des.
Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values are RETAINED.
8.3.1.3.3 1.8 V or 3.3 V VDDIO Operation
The Ser parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V_DDIO) for host compatibility.
The 1.8 V levels will offer lower noise (EMI) and also a system power savings.
8.3.1.4 Ser — Pixel Clock Edge Select (RFB)
The RFB Pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe
set differently. This feature may be controlled by the external Pin or by register.
8.3.1.5 Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
8.3.1.6 Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
8.3.2 Deserializer Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins and strap
Pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balancing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew rate select. The Des features power saving features
with a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
8.3.2.1 Integrated Signal Conditioning Features — Des
8.3.2.1.1 Des — Input Equalizer Gain (Eq)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (ROUT+/-)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external Pin or by
register.
Table 3. Receiver Equalization Configuration
EQ3
L
L
L
L
EQ2
L
L
H
H
INPUTS
EQ1
L
H
L
H
EQ0
H
H
H
H
EFFECT
~1.5 dB
~3 dB
~4.5 dB
~6 dB
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