DS92LV2411_15 Datasheet, PDF (34/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
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8.4 Device Functional Modes
8.4.1 Data Transfer
The DS92LV2411 / DS92LV2412 chipset will transmit and receive a pixel of data in the following format: C1 and
C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The
remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data.
8.4.2 Serializer and Deserializer Operating Modes and Reverse Compatibility (Config[1:0])
The DS92LV2411 / DS92LV2412 chipset is compatible with other single serial lane Channel Link II or FPD-Link II
devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also
the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] Pins on the Ser or Des as
shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or
disabled in the Normal mode. These configuration modes are selectable the control Pins only.
CONFIG1
L
L
H
H
CONFIG0
L
H
L
H
Table 9. DS92LV2411 Serializer Modes
MODE
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Reverse Compatibility Mode
Reverse Compatibility Mode
DES DEVICE
DS92LV2412, DS92LV2412, DS92LV0422,
DS92LV0412
DS92LV2412, DS92LV2412, DS92LV0422,
DS92LV0412
DS90UR124, DS99R124
DS90C124
CONFIG1
L
L
H
H
CONFIG0
L
H
L
H
Table 10. DS92LV2412 Serializer Modes
MODE
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Reverse Compatibility Mode
Reverse Compatibility Mode
SER DEVICE
DS92LV2411, DS92LV2411, DS92LV0421,
DS92LV0411
DS92LV2411, DS92LV2411, DS92LV0421,
DS92LV0411
DS90UR241
DS90C241
8.4.3 Video Control Signal Filter — Serializer and Deserializer
When operating the devices in Normal Mode, the Control Signals have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer.
• Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock
cycles.
Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause
a visual error in display applications. This feature allows for the chipset to validate and filter out any high
frequency noise on the control signals. See Figure.
8.5 Programming
8.5.1 Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap Pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap Pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 30.
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