DS92LV2411_15 Datasheet, PDF (3/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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6 Pin Configuration and Functions
48-Pin WQFN
Package RHS
Top View
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
DI10 37
DI11 38
DI12 39
DI13 40
DI14 41
DI15 42
DI16 43
DI17 44
DI18 45
DI19 46
DI20 47
DI21 48
DS92LV2411
TOP VIEW
DAP = GND
24 VODSEL
23 De-Emph
22 VDDTX
21 PDB
20 DOUT+
19 DOUT-
18 RES2
17 VDDHS
16 RES1
15 RES0
14 VDDP
13 CONFIG[1]
Pin Functions, DS92LV2411 Serializer⁽¹⁾
PIN
NAME
NO.
TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
CI1
5
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI2
3
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI3
4
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
(1) NOTE: 1 = HIGH, 0 = LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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