DS92LV2411_15 Datasheet, PDF (10/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings^(1)(2)(3)
MIN
MAX
UNIT
Supply Voltage – V_DDn (1.8 V)
Supply Voltage – V_DDIO
LVCMOS I/O Voltage
−0.3
2.5
V
−0.3
4.0
V
−0.3
(VDDIO + 0.3)
V
Receiver Input Voltage
−0.3
(VDD + 0.3)
V
Driver Output Voltage
−0.3
(VDD + 0.3)
V
Junction Temperature
+150
°C
Storage Temperature Range (T_stg)
−65
+150
°C
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(3) For soldering specifications, see product folder at www.ti.com and http://www.ti.com/lit/SNOA549
7.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
V_(ESD) Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
Machine Model (MM)
IEC61000–4–2), R_D = 330Ω, C_S = 150pF
Air Discharge (D_OUT+, D_OUT-)
V_(ESD) Electrostatic discharge
Contact Discharge (D_OUT+, D_OUT-)
Air Discharge (R_IN+, D_IN-)
Contact Discharge (R_IN+, R_IN-)
VALUE
±8000
±1000
±250
±2500
±800
±2500
±800
UNIT
V
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken. Pins listed as D_OUT+, D_OUT- or R_IN+, D_IN- may actually have higher
performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken. Pins listed as D_OUT+, D_OUT- or R_IN+, D_IN- may actually have higher
performance.
7.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
Supply Voltage (V_DDn)
LVCMOS Supply Voltage (V_DDIO)
OR
1.71
1.8
1.71
1.8
1.89
V
1.89
V
LVCMOS Supply Voltage (V_DDIO)
Operating Free Air Temperature (T_A)
Clock Frequency
Supply Noise⁽¹⁾
3.0
3.3
−40
+25
5
3.6
V
+85
°C
50
MHz
50
mV_P-P
(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V_DDn (1.8V) supply with
amplitude = 100 mVp-p measured at the device V_DDn Pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter
cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the
noise frequency is less than 400 kHz.
10
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: DS92LV2411 DS92LV2412