DS92LV2411_15 Datasheet, PDF (41/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
the CLKIN. In this example the cable is long, therefore the VODSEL Pin is tied High and a De-Emphasis value is
selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO Pin is
connected also to the 1.8V rail. The optional Serial Bus control is not used in this example, thus the SCL, SDA
and ID[x] Pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until
power is stable.
VDDIO
C9 C7
FB1
C3
LVCMOS
Parallel
Video
Interface
LVCMOS
Control
Interface
C12
DS92LV2411 (SER)
VDDIO
VDDTX
VDDHS
C4
FB2
1.8V
C8 C10
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DI9
DI10
DI11
DI12
DI13
DI14
DI15
VDDP
C11 C5
FB3
VDDL
C6
FB4
C1
DOUT+
DOUT-
C2
Serial
Channel Link II
Interface
DI16
DI17
DI18
DI19
DI20
DI21
DI22
DI23
CLKIN
CI1
CI2
CI3
BISTEN
PDB
CONFIG1
CONFIG0
RFB
VODSEL
De-Emph
ID[X]
SCL
SDA
RES2
RES1
RES0
DAP (GND)
VDDIO
1.8V
R1
10k
RID
NOTE:
C1-C2 = 0.1 PF
C3-C8 = 0.1 PF
C9-11 = 4.7 PF
C12 = >10 PF
R1 (cable specific)
RID (see ID[x] Resistor Value Table 12)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
Figure 35. DS92LV2411 Typical Connection Diagram — Pin Control
Figure 36 shows a typical connection diagram of the DS92LV2412 Des in Pin/strap control mode for a 24-bit
application. The CML inputs utilize 0.1 µF coupling capacitors to the line and the receiver provides internal
termination. Bypass capacitors are placed near the power supply Pins. At a minimum, seven 0.1 µF capacitors
and two 4.7 µF capacitors should be used for local device bypassing. System GPO (General Purpose Output)
signals control the PDB and the BISTEN Pins. In this application the RFB Pin is tied Low to strobe the data on
the falling edge of the CLKOUT.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up resistors are used on the parallel output bus to
select the desired device features. CFEN is set to 1 for Normal Mode with Control Signal Filter enabled, this is
accomplished with the STRAP pull-up on DO23. The receiver input equalizer is also enabled and set to provide
7.5 dB of gain, this is accomplished with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and DO15. To
reduce parallel bus EMI, the SSCG feature is enabled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set to
0010'b and a STRAP pull-up on DO4. The desired features are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO Pin is connected to the 3.3 V
rail. The optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] Pins are left open.
A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
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