DS92LV2411_15 Datasheet, PDF (31/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
PDB
2.0V
LOCK
OP_ LOW
SET
(Strap pin)
OP_ LOW
RELEASE/SET
(Register)
User
controlled
DO[23:0],
CO3, CO2, CO1
TRI-
STATE
ACTIVE
User
controlled
ACTIVE
CLKOUT
TRI-
STATE
ACTIVE
Figure 26. OP_LOW Auto Set
ACTIVE
PDB
2.0V
LOCK
OP_LOW
SET
(Strap pin)
OP_ LOW
RELEASE/SET
(Register)
User
controlled
User
controlled
DO[23:0],
CO3, CO2, CO1
TRI-
STATE
ACTIVE
CLKOUT
TRI-
STATE
ACTIVE
Figure 27. OP_LOW Manual Set/Reset
8.3.2.7 Des — Clock Edge Select (RFB)
The RFB Pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the
Rising edge of the CLKOUT. If RFB is Low, data is strobed on the Falling edge of the CLKOUT. This allows for
inter-operability with downstream devices. The Des output does not need to use the same edge as the Ser input.
This feature may be controlled by the external Pin or by register.
8.3.2.8 Des — Control Signal Filter — Optional
The deserializer provides an optional Control Signal (C3, C2, C1) filter that monitors the three control signals and
eliminates any pulses or glitches that are 1 or 2 parallel clock periods wide. Control signals must be 3 parallel
clock periods wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG[1:0]
strap option or by I2C register control.
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