DS92LV2411_15 Datasheet, PDF (43/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

www.ti.com
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
9.2.2.3 Transmission Media
The Ser/Des chip set is intended to be used in a point-to-point configuration, through a PCB trace, through
twisted pair cable or through 50Ω coaxial cables. The Ser and Des provide internal terminations providing a
clean signaling environment. The interconnect for the differential serial interface should present a differential
impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize
impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment
and application requirements.
For 50Ω coaxial cable serial interfaces, any unused input or output Pin must be terminated with an 0.1 µF AC
coupling capacitor and a 50Ω resistor to ground. The PCB traces and serial interconnect should have a single
ended impedance of 50Ω.
9.2.2.4 Live Link Insertion
The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug
and go” hot insertion capability allows the DS92LV2412 to attain lock to the active data stream during a live
insertion event.
9.2.2.5 Serial Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: http://www.ti.com/ww/en/analog/interface/lvds.shtml
9.2.3 Application Curves
CML
Serializer Data
Throughput
(100 mV/DIV)
50 MHz TX
Pixel Clock
Input
(2 V/DIV)
CML
Serializer Data
Throughput
(100 mV/DIV)
50 MHz TX
Pixel Clock
Input
(2 V/DIV)
Time (4 ns/DIV)
Figure 37. Serializer Output with 50 MHz TX Pixel Clock,
De-emphasis Disabled
Time (4 ns/DIV)
Figure 38. Serializer Output with 50 MHz TX Pixel Clock,
De-emphasis Enabled
Copyright © 2010–2015, Texas Instruments Incorporated
Submit Documentation Feedback
43
Product Folder Links: DS92LV2411 DS92LV2412