DS92LV2411_15 Datasheet, PDF (23/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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Functional Block Diagrams (continued)
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
ROUT+
ROUT-
CMF
RIN+
RIN-
BISTEN
PDB
SCL
SCA
ID[x]
STRAP INPUT
SSCG
LF_MODE
OS_CLKOUT
OS_DATA
OSS_SEL
DO[23:0]
RFB
CO1/DE
CO2/HS
CO3/VS
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
CONFIG [1:0]
EQ
MAP_SEL [1:0]
Timing and
Control
Error
Detector
Clock and
Data
Recovery
DS92LV2412 ± DESERIALIZER
PASS
CLKOUT
LOCK
STRAP INPUT
OP_LOW
8.3 Feature Description
8.3.1 Serializer Functional Description
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external Pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that
provides randomization, scrambling, and DC Balancing of the data. The Ser includes multiple features to reduce
EMI associated with display data transmission. This includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto
stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
8.3.1.1 EMI Reduction Features
8.3.1.1.1 Data Randomization and Scrambling
Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700
MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ).
8.3.1.1.2 Ser — Spread Spectrum Compatibility
The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
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