DS92LV2411_15 Datasheet, PDF (32/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
8.3.2.9 Des — SSCG Low Frequency Optimization (Lf_mode)
Text to come. This feature may be controlled by the external Pin or by Register.
8.3.2.10 Des — Strap Input Pins
Configuration of the device maybe done via configuration input Pins and the STRAP input Pins, or via the Serial
Control Bus. The STRAP input Pins share select parallel bus output Pins. They are used to load in configuration
values during the initial power up sequence of the device. Only a pull-up on the Pin is required when a HIGH is
desired. By default the pad has an internal pull down, and will bias Low by itself. The recommended value of the
pull up is 10 kΩ to V_DDIO; open (NC) for Low, no pull-down is required (internal pull-down). If using the Serial
Control Bus, no pull ups are required.
8.3.3 Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is
useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST
mode only a input clock is required along with control to the Ser and Des BISTEN input Pins. The Ser outputs a
test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.
A PASS output Pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the
test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS
indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration
of the test is controlled by the pulse width applied to the Des BISTEN Pin. During the BIST duration, the
deserializer data outputs toggle with a checkerboard pattern.
Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen 1/2/3).
Note: In order to use BIST mode, the BISTEN Pin must be pulled high and REG = 0. The serializer cannot be
placed in BIST mode if REG = 1, as this will cause the DS92LV2411 to ignore the pin input voltage.
8.3.3.1 Sample BIST Sequence
See Figure 28 for the BIST mode flow diagram.
Step 1: Place the DS92LV2411 Ser in BIST Mode by setting Ser BISTEN = H. For the DS92LV2411 Ser or
DS99R421 Channel Link II Ser BIST Mode is enabled via the BISTEN Pin. A CLKIN is required for BIST. When
the Des detects the BIST mode pattern and command (DCA and DCB code) the data and control signal outputs
are shut off.
Step 2: Place the DS92LV2412 Des in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode
and checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS Pin
will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and
counted to determine the payload error rate.
Step 3: To Stop the BIST mode, the Des BISTEN Pin is set Low. The Des stops checking the data and the final
test result is held on the PASS Pin. If the test ran error free, the PASS output will be High. If there was one or
more errors detected, the PASS output will be Low. The PASS output state is held until a new BIST is run, the
device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN input is set Low. The Link returns to normal
operation.
Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2
shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link
(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting
the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or Rx Equalization).
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