DS92LV2411_15 Datasheet, PDF (21/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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7.12 Typical Characteristics
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
CML Serializer
Data
Throughput
(100 mV/DIV)
50 MHz TX
Pixel Clock
Input
(2 V/DIV)
50 MHz RX
Pixel Clock
Input
(2 V/DIV)
Time (1 ns/DIV)
Time (20 ns/DIV)
Note: On the rising edge of each clock period, the CML driver outputs Note: When both devices are locked and the scope is triggered from
a low Stop bit, high Start bit, and 28 DC-scrambled data bits.
the TX pixel clock, the RX clock is genlocked to the TX pixel clock
Figure 19. Serializer CML Driver Output with 50 MHz TX and does not drift.
Pixel Clock.
Figure 20. Comparison of Deserializer LVCMOS RX Clock
Output locked to a 50 MHz TX Pixel Clock.
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