DS92LV2411_15 Datasheet, PDF (38/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
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ADD ADD REGISTER
(dec) (hex)
NAME
0
0 Des Config 1
1
1 Slave ID
2
2 Des Features 1
Table 14. Deserializer — Serial Bus Control Registers
Bit(s) R/W
7
R/W
6
R/W
5
R/W
4
R/W
3:2 R/W
1
R/W
0
R/W
7
R/W
6:0 R/W
7
R/W
6
R/W
5:4 R/W
3
R/W
2:0 R/W
DEFAULT
(bin)
0
FUNCTION
LF_MODE
0
OS_CLKOUT
0
OS_DATA
0
RFB
00
CONFIG
0
SLEEP
0
REG Control
0
1110000 ID[X]
0
OP_LOW
0
OSS_SEL
00
Reserved
0
OP_LOW Strap
Bypass
00
OSC_SEL
DESCRIPTION
0: 20 to 50 MHz SSCG Operation
1: 5 to 20 MHz SSCG Operation
0: Normal CLKOUT Slew Rate
1: Increased CLKOUT Slew Rate
0: Normal DATA Slew Rate
1: Increased DATA Slew Rate
0: Data strobed on Falling edge of CLKOUT
1: Data strobed on Rising edge of CLKOUT
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Reserved
11: Reserved
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0: Configurations set from control Pins / STRAP
Pins
1: Configurations set from registers (except I2C_ID)
0: Address from ID[X] Pin
1: Address from Register
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
0: Set outputs state LOW (except LOCK)
1: Release output LOW state, outputs toggling
normally
Note: This register only works during LOCK = 1
Output Sleep State Select
0: CLKOUT, DO[23:0], CO1, CO2, CO3 = L, LOCK
= Normal, PASS = H
1: CLKOUT, DO[23:0], CO1, CO2, CO3 = Tri-State,
LOCK = Normal, PASS = H
Reserved
0: Strap will determine whether OP_LOW feature is
ON or OFF
1: Turns OFF OP_LOW feature
000: disable
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
38
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