DS92LV2411_15 Datasheet, PDF (19/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
7.10 Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
t_LHT
Ser Output Low-to-High
R_L = 100Ω, De-emphasis = disabled,
Transition Time, Figure 3 VODSEL = 0
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
t_HLT
Ser Output High-to-Low
R_L = 100Ω, De-emphasis = disabled,
Transition Time, Figure 3 VODSEL = 0
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
t_DIS
Input Data - Setup Time, DI[23:0], CI1, CI2, CI3 to CLKIN
Figure 4
t_DIH
Input Data - Hold Time,
CLKIN to DI[23:0], CI1, CI2, CI3
Figure 4
t_XZD
Ser Output Active to OFF
Delay, Figure 6
t_PLD
Serializer PLL Lock Time⁽¹⁾, R_L = 100Ω
Figure 5
t_SD
Serializer Delay - Latency, R_L = 100Ω
Figure 7
t_DJIT
Ser Output Total Jitter,
R_L = 100Ω, De-Emph = disabled,
Figure 8
RANDOM pattern, CLKIN = 50 MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 5MHz
λ_STXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
CLKIN = 50 MHz
CLKIN = 43 MHz
CLKIN = 20 MHz
CLKIN = 5MHz
δ_STX
Serializer Jitter Transfer
Function Peaking
CLKIN = 50 MHz
CLKIN = 43 MHz
CLKIN = 20 MHz
CLKIN = 5MHz
MIN TYP MAX UNIT
200
ps
200
ps
200
ps
200
ps
2
ns
2
ns
8
15 ns
1.4
10 ms
144*T 145*T ns
0.28
UI
0.27
UI
0.35
UI
3
MHz
2.3
MHz
1.3
MHz
650
kHz
0.84
dB
0.83
dB
0.83
dB
0.28
dB
(1) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require t_PLD
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