DS92LV2411_15 Datasheet, PDF (7/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Pin Functions, DS92LV2412 Deserializer ⁽¹⁾ (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
CO2
8
O, LVCMOS Control Signal Output
For Display/Video Application:
CO2 = Horizontal Sync Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
CO3
7
O, LVCMOS Control Signal Output
For Display/Video Application:
CO3 = Vertical Sync Output
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.
Thus, the minimum pulse width allowed is 130 clock cycle wide.
The CONFIG[1:0] Pins have no affect on CO3 signal
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
DO[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP,
O, LVCMOS
Parallel Interface Data Output Pins
For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
DO[15:8]
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP,
O, LVCMOS
Parallel Interface Data Output Pins
For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
DO[23:16]
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP,
O, LVCMOS
Parallel Interface Data Input Pins
For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 6). These
Pins are inputs during power-up (See STRAP Inputs).
LOCK
32
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,
CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 6). May be
used as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
CONTROL AND CONFIGURATION — STRAP PINS ⁽²⁾
CONFIG[1:0]
10 [DO22],
9 [DO23]
STRAP
I, LVCMOS
w/ pull-down
00: Control Signal Filter DISABLED. Interfaces with DS92LV2411 or DS92LV0411
01: Control Signal Filter ENABLED. Interfaces with DS92LV2411 or DS92LV0411
10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241
11: Reverse compatibility mode to interface with the DS90C241
EQ[3:0]
20 [DO15],
21 [DO14],
22 [DO13],
23 [DO12]
STRAP Receiver Input Equalization
I, LVCMOS (See Table 3).
w/ pull-down This can also be controlled by I2C register access.
LF_MODE
12 [DO20]
STRAP
I, LVCMOS
w/ pull-down
SSCG Low Frequency Mode
Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz)
This can also be controlled by I2C register access.
MAP_SEL[1:0]
40[D],
41 [D]
STRAP Bit mapping reverse compatibility / DS90UR241 Options
I, LVCMOS Pin or Register Control
w/ pull-down Default setting is b'00.
(2) For a High State, use a 10 kΩ pull up to V_DDIO; for a Low State, the IO includes an internal pull down. The STRAP Pins are read upon
power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.
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