DS92LV2411_15 Datasheet, PDF (33/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 28. BIST Mode Flow Diagram
8.3.3.2 BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we
assume a 50 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.39 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK Pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK Pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS Pin provides a powerful tool for system evaluation and
performance monitoring.
BISTEN
(SER)
BISTEN
(DES)
CLKOUT
(RFB = L)
DO[23:0]
CO1,CO2,CO3
DATA
(internal)
PASS
Prior Result
DATA
X
(internal)
PASS
Prior Result
Normal
PRBS
X = bit error(s)
X
X
BIST Test
BIST Duration
PASS
FAIL
BIST
Result
Held
Normal
Figure 29. BIST Waveforms
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