DS92LV2411_15 Datasheet, PDF (28/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
8.3.2.4 Des — Clock-Data Recovery Status Flag (Lock) And Output State Select (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
LOW (depending on the value of the OSS_SEL setting). After the DS92LV2412 completes its lock sequence to
the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial
input is available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the
change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven Low and the state of the outputs are based
on the OSS_SEL setting (STRAP Pin configuration or register).
8.3.2.5 Des — Oscillator Output — Optional
The Des provides an optional clock output when the input clock (serial stream) has been lost. This is based on
an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled by the
external Pin or by register. See Table 7 and Table 8.
SERIAL
INPUT
X
X
Static
Static
Active
Table 6. OSS_SEL And PDB Configuration — Des Outputs
INPUTS
PDB
L
L
H
H
H
OUTPUTS
OSS_SEL
CLKOUT
DO[23:0], CO1,
CO2, CO3
LOCK
L
Z
Z
Z
H
Z
Z
Z
L
L
L
L
H
Z
Z*
L
X
Active
Active
H
*NOTE — If Pin is strapped HIGH the output will be pulled up
PASS
Z
Z
L
L
H
Table 7. OSC (Oscillator) Mode — Des Output
INPUTS
EMBEDDED CLK
CLKOUT
NOTE *
OSC
Output
Present
Toggling
* NOTE — Absent and OSC_SEL ≠ 000
OUTPUTS
DO[23:0]/CO1/CO2/CO3
L
Active
LOCK
L
H
PASS
H
H
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