DS92LV2411_15 Datasheet, PDF (8/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
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Pin Functions, DS92LV2412 Deserializer ⁽¹⁾ (continued)
PIN
NAME
NO.
TYPE
DESCRIPTION
OP_LOW
42 [PASS]
STRAP
I, LVCMOS
w/ pull-down
Outputs held LOW when LOCK = 1
NOTE: Do not use any other strap options with this strap function enabled
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE
See Figure 26 and Figure 27
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
OS_CLKOUT
11 [DO21]
STRAP
I, LVCMOS
w/ pull-down
Output CLKOUT Slew Select
OS_CLKOUT = 1, Increased CLKOUT slew rate
OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
OS_DATA
14 [DO19]
STRAP
I, LVCMOS
w/ pull-down
Output DO[23:0], CO1, CO2, CO3 Slew Select
OS_DATA = 1, Increased DO slew rate
OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
OSS_SEL
17 [DO18]
STRAP
I, LVCMOS
w/ pull-down
Output Sleep State Select
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
Down (Sleep). (See Table 6).
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
RFB
18 [DO17]
STRAP
I, LVCMOS
w/ pull-down
Clock Output Strobe Edge Select
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
OSC_SEL[2:0] 26 [DO10], STRAP Oscillator Selectl
27 [DO9], I, LVCMOS (See Table 7 and Table 8).
28 [DO8] w/ pull-down This can also be controlled by I2C register access.
SSC[3:0]
34 [DO6],
35 [DO5],
36 [DO4],
37 [DO3]
STRAP Spread Spectrum Clock Generation (SSCG) Range Select
I, LVCMOS (See Table 4 and Table 5).
w/ pull-down This can also be controlled by I2C register access.
CONTROL AND CONFIGURATION
BISTEN
44
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
ID[x]
56
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 11).
NC
1, 15, 16,
30, 31, 45,
46, 60
Not Connected
Leave Pin open (float)
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by
Table 6. Control Registers are RESET.
RES
47
I, LVCMOS Reserved - tie LOW
w/ pull-down
SCL
3
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
Open Drain SCL requires an external pull-up resistor to 3.3V.
SDA
2
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor to 3.3V.
8
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