DS92LV2411_15 Datasheet, PDF (27/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Table 5. SSCG Configuration (Lf_mode = H) — Des Output
SSC[3:0] INPUTS
LH_MODE = H (5 - 20 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
RESULT
fdev (%)
NA
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
fmod (kHz)
Disable
CLK/620
CLK/370
CLK/258
CLK/192
Frequency
F_CLKOUT+
F_CLKOUT
F_CLKOUT-
fdev(max)
fdev(min)
1/fmod
Time
Figure 22. SSCG Waveform
8.3.2.2.4 1.8 V or 3.3 V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate with 1.8 V or 3.3 V levels (V_DDIO) for target host
compatibility. The 1.8 V levels will offer a lower noise (EMI) and also a system power savings.
8.3.2.3 Power Saving Features
8.3.2.3.1 Des — Powerdown Feature (PDB)
The Des has a PDB input Pin to ENABLE or POWER DOWN the device. This Pin can be controlled by the
system to save power, disabling the Des when the display is not needed. An auto detect mode is also available.
In this mode, the PDB Pin is tied High and the Des will enter POWER DOWN when the serial stream stops.
When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK Pin and output
valid data. In POWER DOWN mode, the Data and CLKOUT output states are determined by the OSS_SEL
status. Note – in POWER DOWN, the optional Serial Bus Control Registers are RESET.
8.3.2.3.2 Des — Stop Stream Sleep Feature
The Des will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then
lock to the incoming signal and recover the data. Note – in STOP STREAM SLEEP, the optional Serial Bus
Control Registers values are RETAINED.
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