DS92LV2411_15 Datasheet, PDF (6/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
60-Pin WQFN
Package NKB
Top View
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NC 46
RES 47
VDDIR 48
RIN+ 49
RIN- 50
CMF 51
ROUT+ 52
ROUT- 53
VDDCMLO 54
VDDR 55
ID[x] 56
VDDPR 57
VDDSC 58
PDB 59
NC 60
DS92LV2412
TOP VIEW
DAP = GND
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
30 NC
29 VDDL
28 DO8/OSC_SEL0
27 DO9/OSC_SEL1
26 DO10/OSC_SEL2
25 DO11
24 VDDIO
23 DO12/EQ0
22 DO13/EQ1
21 DO14/EQ2
20 DO15/EQ3
19 DO16
18 DO17/RFB
17 DO18/OSS_SEL
16 NC
Pin Functions, DS92LV2412 Deserializer ⁽¹⁾
PIN
NAME
NO.
TYPE
DESCRIPTION
LVCMOS PARALLEL INTERFACE
CLKOUT
5
O, LVCMOS Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). Data
strobe edge set by RFB.
CO1
6
O, LVCMOS Control Signal Output
For Display/Video Application:
CO1 = Data Enable Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).
(1) NOTE: 1 = HIGH, 0 = LOW
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
6
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