DS92LV2411_15 Datasheet, PDF (45/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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Layout Example (continued)
DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
Figure 39. No Pullback LLP, Single Row Reference Diagram
Table 16. No Pullback LLP Stencil Aperture Summary for DS92LV2411 and DS92LV2412
Device
Pin MKT Dwg PCB I/O
Count
Pad Size
(mm)
PCB
Pitch
(mm)
DS92LV2411 48
SQA48A
0.25 x
0.6
0.5
DS92LV2412 60
SQA60B
0.25 x
0.8
0.5
PCB DAP
size (mm)
5.1 x 5.1
7.2 x 7.2
Stencil I/O
Aperture
(mm)
0.25 x 0.7
Stencil DAP
Aperture
(mm)
Number of
DAP
Aperture
Openings
Gap Between DAP
Aperture (Dim A
mm)
1.1 x 1.1
16
0.2
0.25 x 0.9 1.16 x 1.16
25
0.3
Figure 40. 48-Pin WQFN Stencil Example of Via and Opening Placement
The following PCB layout examples are derived from the layout design of the DS9LV2411 and DS92LV2412 in
the LV24EVK01 Evaluation Module User's Guide (SNLU006). These graphics and additional layout description
are used to demonstrate both proper routing and proper solder techniques when designing in the Ser/Des pair.
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