DS92LV2411_15 Datasheet, PDF (40/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
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9 Applications and Implementation
9.1 Application Information
The DS92LV2411/DS92LV2412 chipset is intended for interface between a host (graphics processor) and a
Display. It supports an 24-bit color depth (RGB888). In a RGB888 application, 24 color bits (D[23:0), Pixel Clock
(CLKIN) and three control bits (C1, C2, C3) are supported across the serial link with CLK rates from 5 to 50 MHz.
The chipset may also be used in 18-bit color applications. In this application three to six general purpose signals
may also be sent from host to display.
The Des is expected to be located close to its target device. The interconnect between the Des and the target
device is typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to
be in the 5 to 10 pF range. Care should be taken on the CLK output trace as this signal is edge sensitive and
strobes the data. It is also assumed that the fanout of the Des is one. If additional loads need to be driven, a
logic buffer or mux device is recommended.
9.2 Typical Applications
V_DDIO V_DDn
(1.8V or 3.3V) 1.8V
V_DDn V_DDIO
1.8V (1.8V or 3.3V)
Graphic
Processor
OR
Video
Imager
OR
ASIC/FPGA
DI[7:0]
DI[15:8]
DI[23:16]
CI1
CI2
CI3
CLKIN
PDB
BISTEN
Optional
SCL
SDA
ID[x]
DOUT+
DOUT-
DS92LV2411
Serializer
DAP
Channel Link II
1 Pair /AC Coupled
0.1 2F
0.1 2F
100 ohm STP Cable
CMF
RFB
VODSEL
DeEmph
Optional
PDB
BISTEN
SCL
SDA
ID[x]
RIN+
RIN-
DS92LV2412
Deserializer
DAP
DO[7:0]
DO[15:8]
DO[23:16]
CO1
CO2
CO3
CLKOUT
LOCK
PASS
STRAP pins
not shown
24-bit RGB
Display
OR
ASIC/FPGA
Figure 34. Typical Application Schematic for DS92LV2411, DS92LV2412 Ser/Des Pair
9.2.1 Design Requirements
For this typical design application, use the following as input parameters.
Table 15. Design Parameters
DESIGN PARAMETER
VDDIO
VDDn
AC Coupling Capacitor for DOUT± and RIN±
CLK Frequency
EXAMPLE VALUE
1.8 V or 3.3 V
1.8 V
0.1 µF
50 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Typical Application Connection
Figure 35 shows a typical connection diagram of the DS92LV2411 Ser in Pin control mode for a 24-bit
application. The CML outputs require 0.1 µF AC coupling capacitors to the line. The line driver includes internal
termination. Bypass capacitors are placed near the power supply Pins. At a minimum, four 0.1 µF capacitors and
a 4.7 µF capacitor should be used for local device bypassing. System GPO (General Purpose Output) signals
control the PDB and BISTEN Pins. In this application the RFB Pin is tied Low to latch data on the falling edge of
40
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