DS92LV2411_15 Datasheet, PDF (22/54 Pages) Texas Instruments – 5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

DS92LV2411, DS92LV2412
SNLS302E – MAY 2010 – REVISED FEBRUARY 2015
www.ti.com
8 Detailed Description
8.1 Overview
The DS92LV2411 / DS92LV2412 chipset transmits and receives 24-bits of data and 3 control signals over a
single serial CML pair operating at 140 Mbps to 1.4 Gbps. The serial stream also contains an embedded clock,
video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display or ASIC/FPGA.
The DS92LV2411 / DS92LV2412 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the
serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the
serial bit stream (restrictions apply) along with six additional general purpose signals.
8.2 Functional Block Diagrams
VODSEL
De-Emph
DI[23:0]
CI1/DE
CI2/HS
CI3/VS
RFB
CLKIN
CONFIG[1:0]
PDB
SCL
SCA
ID[x]
BISTEN
PLL
Pattern
Generator
Timing and
Control
DS92LV2411 ± SERIALIZER
DOUT+
DOUT-
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