COP8SGE5_14 Datasheet, PDF (9/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
AC Electrical Characteristics
−40°C ≤ T_A ≤ +85°C unless otherwise specified.
Parameter
Conditions
Instruction Cycle Time (t_C)⁽¹⁾
Crystal/Resonator, External
4.5V ≤ V_CC ≤ 5.5V
2.7V ≤ V_CC ≤ 4.5V
R/C Oscillator (Internal)
Frequency Variation⁽²⁾
External CKI Clock Duty Cycle⁽²⁾
4.5V ≤ V_CC ≤ 5.5V
4.5V ≤ V_CC ≤ 5.5V
fr = Max
Rise Time⁽²⁾
fr = 10 MHz Ext Clock
Fall Time⁽²⁾
fr = 10 MHz Ext Clock
MICROWIRE Setup Time (t_UWS)⁽³⁾
MICROWIRE Hold Time (t_UWH)⁽³⁾
MICROWIRE Output Propagation Delay
(t_UPD) ⁽³⁾
Input Pulse Width⁽²⁾
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3, Input High Time
Timer 1 2, 3, Input Low Time
Reset Pulse Width
Min
Typ
0.67
2
2
±35
45
20
56
1
1
1
1
1
Max
55
8
5
220
Units
μs
μs
μs
%
%
ns
ns
ns
ns
ns
t_C
t_C
t_C
t_C
μs
(1) t_C = Instruction cycle time.
(2) Parameter characterized but not tested.
(3) MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See
Figure 8 and the MICROWIRE operation description.
Comparators AC and DC Characteristics
V_CC = 5V, −40°C ≤ T_A ≤ +85°C.
Parameter
Input Offset Voltage⁽¹⁾
Input Common Mode Voltage Range
Conditions
0.4V ≤ V_IN ≤ V_CC − 1.5V
Voltage Gain
Low Level Output Current
High Level Output Current
DC Supply Current per Comparator (When Enabled)
Response Time⁽²⁾
Comparator Enable Time⁽³⁾
V_OL = 0.4V
V_OH = V_CC − 0.4V
200 mV step input
100 mV Overdrive,
100 pF Load
Min
Typ
±5
0.4
100
−1.6
1.6
Max
±15
V_CC − 1.5
150
600
600
Units
mV
V
dB
mA
mA
μA
ns
ns
(1) The comparator inputs are high impedance port inputs and, as such, input current is limited to port input leakage current.
(2) Response time is measured from a step input to a valid logic level at the comparator output. software response time is dependent of
instruction execution.
(3) Comparator enable time is that delay time required between the end of the instruction cycle that enables the comparator and using the
output of the comparator, either by hardware or by software.
Figure 8. MICROWIRE/PLUS Timing
Copyright © 2000–2013, Texas Instruments Incorporated
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