COP8SGE5_14 Datasheet, PDF (48/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
VIS Execution
When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even
number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest
arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is
active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FA is
generated and so forth. If the only active interrupt is software trap, than E0 is generated. This number replaces
the lower byte of the PC. The upper byte of the PC remains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration ranking. This vector is read from program memory and
placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the
highest arbitration ranking.
Figure 35 illustrates the different steps performed by the VIS instruction. Figure 36 shows a flowchart for the VIS
instruction.
The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction
(under certain conditions) and upon RESET.
Figure 35. VIS Operation
48
Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7