COP8SGE5_14 Datasheet, PDF (40/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
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USART INTERRUPTS
The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit
Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are
reserved for each interrupt vector. The two vectors are located at addresses 0xEC to 0xEF Hex in the program
memory space. The interrupts can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and
Enable Receive Interrupt (ERI) bits in the ENUI register.
The interrupt from the Transmitter is set pending, and remains pending, as long as both the TBMT and ETI bits
are set. To remove this interrupt, software must either clear the ETI bit or write to the TBUF register (thus
clearing the TBMT bit).
The interrupt from the receiver is set pending, and remains pending, as long as both the RBFL and ERI bits are
set. To remove this interrupt, software must either clear the ERI bit or read from the RBUF register (thus clearing
the RBFL bit).
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of the USART can be individually selected to come
either from an external source at the CKX pin (port L, pin L1) or from a source selected in the PSR and BAUD
registers. Internally, the basic baud clock is created from the oscillator frequency through a two-stage divider
chain consisting of a 1–16 (increments of 0.5) prescaler and an 11-bit binary counter. (Figure 32). The divide
factors are specified through two read/write registers shown in Figure 33. Note that the 11-bit Baud Rate Divisor
spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.
As shown in Table 6, a Prescaler Factor of 0 corresponds to NO CLOCK. This condition is the USART power
down mode where the USART clock is turned off for power saving purpose. The user must also turn the USART
clock off when a different baud rate is chosen.
The correspondences between the 5-bit Prescaler Select and Prescaler factors are shown in Table 6. There are
many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a
1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive the
software programmable baud rate counter to create a 16x clock for the following baud rates: 110, 134.5, 150,
300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 (Table 5). Other baud rates may be
created by using appropriate divisors. The 16x clock is then divided by 16 to provide the rate for the serial shift
registers of the transmitter and receiver.
Figure 32. USART BAUD Clock Generation
Figure 33. USART BAUD Clock Divisor Registers
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