COP8SGE5_14 Datasheet, PDF (28/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
The IDLE Timer T0 can generate an interrupt when the twelfth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 2.731 ms at the maximum clock frequency (t_C = 0.67 μs). A control flag T0EN
allows the interrupt from the twelfth bit of Timer T0 to be enabled or disabled. Setting T0EN will enable the
interrupt, while resetting it will disable the interrupt.
TIMER T1, TIMER T2 and TIMER T3
Each device have a set of three powerful timer/counter blocks, T1, T2 and T3. Since T1, T2, and T3 are
identical, all comments are equally applicable to any of the three timer blocks which will be referred to as Tx.
Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O required by the
timer block, while the pin TxB is an input to the timer block. The timer block has three operating modes:
Processor Independent PWM mode, External Event Counter mode, and Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.
Mode 1. Processor Independent PWM Mode
One of the timer's operating modes is the Processor Independent PWM mode. In this mode, the timer generates
a “Processor Independent” PWM signal because once the timer is setup, no more action is required from the
CPU which translates to less software overhead and greater throughput. The user software services the timer
block only when the PWM parameters require updating. This capability is provided by the fact that the timer has
two separate 16-bit reload registers. One of the reload registers contains the “ON” timer while the other holds the
“OFF” time. By contrast, a microcontroller that has only a single reload register requires an additional software to
update the reload value (alternate between the on-time/off-time).
The timer can generate the PWM output with the width and duty cycle controlled by the values stored in the
reload registers. The reload registers control the countdown values and the reload values are automatically
written into the timer when it counts down through 0, generating interrupt on each reload. Under software control
and with minimal overhead, the PMW outputs are useful in controlling motors, triacs, the intensity of displays,
and in providing inputs for data acquisition and sine wave generators.
In this mode, the timer Tx counts down at a fixed rate of t_C. Upon every underflow the timer is alternately
reloaded with the contents of supporting registers, RxA and RxB. The very first underflow of the timer causes the
timer to reload from the register RxA. Subsequent underflows cause the timer to be reloaded from the registers
alternately beginning with the register RxB.
Figure 24 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to
generate interrupts.
Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must
reset these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the
interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag TxENA will cause an
interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable
flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer.
Resetting the timer enable flags will disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose
to interrupt on both edges of the PWM output.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin. The Tx timer control bits, TxC3, TxC2 and TxC1
allow the timer to be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer
are latched into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer
underflows.
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