COP8SGE5_14 Datasheet, PDF (47/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and
may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to
the execution of the VIS instruction, such as executing a single cycle instruction which clears an enable flag at
the same time that the pending flag is set. It can also result, however, from inadvertent execution of the VIS
command outside of the context of an interrupt.
The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur during
the servicing of another interrupt. Rather than restoring the program context (A, B, X, etc.) and executing the
RETI instruction, an interrupt service routine can be terminated by returning to the VIS instruction. In this case,
interrupts will be serviced in turn until no further interrupts are pending and the default VIS routine is started.
After testing the GIE bit to ensure that execution is not erroneous, the routine should restore the program context
and execute the RETI to return to the interrupted program.
This technique can save up to fifty instruction cycles (t_c), or more, (50µs at 10 MHz oscillator) of latency for
pending interrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending.
To ensure reliable operation, the user should always use the VIS instruction to determine the source of an
interrupt. Although it is possible to poll the pending bits to detect the source of an interrupt, this practice is not
recommended. The use of polling allows the standard arbitration ranking to be altered, but the reliability of the
interrupt system is compromised. The polling routine must individually test the enable and pending bits of each
maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have
the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced, resulting in an
inadvertent “locking out” of all maskable interrupts by the Software Trap pending flag. Problems such as this can
be avoided by using VIS instruction.
Table 7. Interrupt Vector Table
Arbitration Ranking
Source
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
Software
Reserved
External
Timer T0
Timer T1
Timer T1
MICROWIRE/PLUS
Reserved
USART
USART
Timer T2
Timer T2
Timer T3
Timer T3
Port L/Wakeup
Default VIS
Description
INTR Instruction
G0
Underflow
T1A/Underflow
T1B
BUSY Low
Receive
Transmit
T2A/Underflow
T2B
T2A/Underflow
T3B
Port L Edge
Reserved
Vector Address⁽¹⁾
(Hi-Low Byte)
0yFE–0yFF
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
0yF6–0yF7
0yF4–0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0yEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
(1) y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is
located at the last address of a block. In this case, the table must be in the next block.
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