COP8SGE5_14 Datasheet, PDF (36/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
DESCRIPTION OF USART REGISTER BITS
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ENU-USART Control and Status Register (Address at 0BA)
PEN
Bit 7
PSEL1
XBIT9/
PSEL0
CHL1
CHL0
ERR
RBFL
TBMT
Bit 0
PEN: This bit enables/disables Parity (7- and 8-bit modes only). Read/Write, cleared on reset.
PEN = 0 Parity disabled.
PEN = 1 Parity enabled.
PSEL1, PSEL0: Parity select bits. Read/Write, cleared on reset.
PSEL1 = 0, PSEL0 = 0 Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL0 = 1 Even Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0 Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL0 = 1 Space(0) (if Parity enabled)
XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits per
frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity. Read/Write,
cleared on reset.
CHL1, CHL0: These bits select the character frame format. Parity is not included and is generated/verified by
hardware. Read/Write, cleared on reset.
CHL1 = 0, CHL0 = 0 The frame contains eight data bits.
CHL1 = 0, CHL0 = 1 The frame contains seven data bits.
CHL1 = 1, CHL0 = 0 The frame contains nine data bits.
CHL1 = 1, CHL0 = 1 Loopback Mode selected. Transmitter output internally looped back to receiver input. Nine
bit framing format is used.
ERR: This bit is a global USART error flag which gets set if any or a combination of the errors (DOE, FE, PE)
occur. Read only; it cannot be written by software, cleared on reset.
RBFL: This bit is set when the USART has received a complete character and has copied it into the RBUF
register. It is automatically reset when software reads the character from RBUF. Read only; it cannot be written
by software, cleared on reset.
TBMT: This bit is set when the USART transfers a byte of data from the TBUF register into the TSFT register for
transmission. It is automatically reset when software writes into the TBUF register. Read only, bit is set to “one”
on reset; it cannot be written by software.
ENUR-USART Receive Control and Status Register
(Address at 0BB)
DOE
Bit 7
FE
PE
Reserved ⁽¹⁾
(1) Bit is reserved for future use. User must set to zero.
RBIT9
ATTN
XMTG
RCVG
Bit 0
DOE: Flags a Data Overrun Error. Read only, cleared on read, cleared on reset.
DOE = 0 Indicates no Data Overrun Error has been detected since the last time the ENUR register was read.
DOE = 1 Indicates the occurrence of a Data Overrun Error.
FE: Flags a Framing Error. Read only, cleared on read, cleared on reset.
FE = 0 Indicates no Framing Error has been detected since the last time the ENUR register was read.
FE = 1 Indicates the occurrence of a Framing Error.
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