COP8SGE5_14 Datasheet, PDF (27/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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T2CNTRL Register (Address X′00C6)
T2C3
Bit 7
T2C2
T2C1
T2C0
COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
T2PNDA
T2ENA
T2PNDB
T2ENB
Bit 0
The T2CNTRL control register contains the following bits:
T2C3 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C1 Timer T2 mode control bit
T2C0 Timer T2 Start/Stop control in timer modes 1 and 2, T2 Underflow Interrupt Pending Flag in timer
mode 3
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A capture
edge in mode 3)
T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
T2ENB Timer T2 Interrupt Enable for Timer Underflow or T2B Input capture edge
T3CNTRL Register (Address X′00B6)
T3C3
Bit 7
T3C2
T3C1
T3C0
T3PNDA
T3ENA
T3PNDB
T3ENB
Bit 0
The T3CNTRL control register contains the following bits:
T3C3 Timer T3 mode control bit
T3C2 Timer T3 mode control bit
T3C1 Timer T3 mode control bit
T3C0 Timer T3 Start/Stop control in timer modes 1 and 2, T3 Underflow Interrupt Pending Flag in timer
mode 3
T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA in mode 1, T3 Underflow in mode 2, T3A capture
edge in mode 3)
T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A Input capture edge
T3PNDB Timer T3 Interrupt Pending Flag for T3B capture edge
T3ENB Timer T3 Interrupt Enable for Timer Underflow or T3B Input capture edge
Timers
Each device contains a very versatile set of timers (T0, T1, T2 and T3). Timer T1, T2 and T3 and associated
autoreload/capture registers power up containing random data.
TIMER T0 (IDLE TIMER)
Each device supports applications that require maintaining real time and low power with the IDLE mode. This
IDLE mode support is furnished by the IDLE timer T0. The Timer T0 runs continuously at the fixed rate of the
instruction cycle clock, t_C. The user cannot read or write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
• Exit out of the Idle Mode (See Idle Mode description)
• WATCHDOG logic (See WATCHDOG description)
• Start up delay out of the HALT mode
• Timing the width of the internal power-on-reset
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Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7