COP8SGE5_14 Datasheet, PDF (57/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
Figure 40. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High
Figure 41. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High
Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address
S/ADD REG
0000 to 006F
0070 to 007F
xx80 to xx93
xx94
xx95
xx96
xx97 to xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
Contents ⁽¹⁾
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads As All Ones)
Unused RAM Address Space (Reads Undefined Data)
Port F data register, PORTFD
Port F configuration register, PORTFC
Port F input pins (read only), PORTFP
Unused address space (Reads Undefined Data)
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA Lower Byte
Timer T3 Autoload Register T3RA Upper Byte
Timer T3 Autoload Register T3RB Lower Byte
Timer T3 Autoload Register T3RB Upper Byte
Timer T3 Control Register
Comparator Select Register (Reg:CMPSL)
UART Transmit Buffer (Reg:TBUF)
UART Receive Buffer (Reg:RBUF)
UART Control and Status Register (Reg:ENU)
UART Receive Control and Status Register (Reg:ENUR)
UART Interrupt and Clock Source Register (Reg:ENUI)
UART Baud Register (Reg:BAUD)
(1) Reading memory locations 0070H–007FH (Segment 0) will return all ones. Reading unused memory
locations 0080H–0093H (Segment 0) will return undefined data. Reading memory locations from other
Segments (i.e., Segment 4, Segment 5, … etc.) will return undefined data.
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Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7