COP8SGE5_14 Datasheet, PDF (14/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
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Pin Descriptions
The COP8SGx I/O structure enables designers to reconfigure the microcontroller's I/O functions with a single
instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with
high impedance or input with weak pull-up device. A typical example is the use of I/O pins as the keyboard
matrix input lines. The input lines can be programmed with internal weak pull-ups so that the input lines read
logic high when the keys are all open. With a key closure, the corresponding input line will read a logic zero since
the weak pull-up can easily be overdriven. When the key is released, the internal weak pull-up will pull the input
line back to logic high. This eliminates the need for external pull-up resistors. The high current options are
available for driving LEDs, motors and speakers. This flexibility helps to ensure a cleaner design, with less
external components and lower costs. Below is the general description of all available pins.
V_CC and GND are the power supply pins. All V_CC and GND pins must be connected.
CKI is the clock input. This can come from the Internal R/C oscillator, external, or a crystal oscillator (in
conjunction with CKO). See Oscillator Description section.
RESET is the master reset input. See Reset description section.
Each device contains four bidirectional 8-bit I/O ports (C, G, L and F), where each individual bit may be
independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under
program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port
has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA
register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory map
for the various addresses associated with the I/O ports.) Figure 13 shows the I/O port configurations. The DATA
and CONFIGURATION registers allow for each port bit to be individually configured under software control as
shown below:
CONFIGURATION Register
0
0
1
1
DATA
Register
0
1
0
1
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.
Port L supports the Multi-Input Wake Up feature on all eight pins. Port L has the following alternate pin functions:
L7 Multi-input Wakeup or T3B (Timer T3B Input)
L6 Multi-input Wakeup or T3A (Timer T3A Input)
L5 Multi-input Wakeup or T2B (Timer T2B Input)
L4 Multi-input Wakeup or T2A (Timer T2A Input)
L3 Multi-input Wakeup and/or RDX (USART Receive)
L2 Multi-input Wakeup or TDX (USART Transmit)
L1 Multi-input Wakeup and/or CKX (USART Clock)
L0 Multi-input Wakeup
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O ports. Pin G6 is always a general purpose Hi-Z input.
All pins have Schmitt Triggers on their inputs.Pin G1 serves as the dedicated WATCHDOG output with weak
pullup if WATCHDOG feature is selected by the Mask Option register. The pin is a general purpose I/O if
WATCHDOG feature is not selected. If WATCHDOG feature is selected, bit 1 of the Port G configuration and
data register does not have any effect on Pin G1 setup. Pin G7 is either input or output depending on the
oscillator option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for
the CKO clock output. With the internal R/C or the external oscillator option selected, G7 serves as a general
purpose Hi-Z input pin and is also used to bring the device out of HALT mode with a low to high transition on G7.
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