COP8SGE5_14 Datasheet, PDF (38/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
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Associated I/O Pins
Data is transmitted on the TDX pin and received on the RDX pin. TDX is the alternate function assigned to Port L
pin L2; it is selected by setting ETDX (in the ENUI register) to one. RDX is an inherent function of Port L pin L3,
requiring no setup.
The baud rate clock for the USART can be generated on-chip, or can be taken from an external source. Port L
pin L1 (CKX) is the external clock I/O pin. The CKX pin can be either an input or an output, as determined by
Port L Configuration and Data registers (Bit 1). As an input, it accepts a clock signal which may be selected to
drive the transmitter and/or receiver. As an output, it presents the internal Baud Rate Generator output.
USART Operation
The USART has two modes of operation: asynchronous mode and synchronous mode.
ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to the USART
is 16 times the baud rate.
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current
character on the TDX pin, the TBUF register may be loaded by software with the next byte to be transmitted.
When TSFT finishes transmitting the current character the contents of TBUF are transferred to the TSFT register
and the Transmit Buffer Empty Flag (TBMT in the ENU register) is set. The TBMT flag is automatically reset by
the USART when software loads a new character into the TBUF register. There is also the XMTG bit which is set
to indicate that the USART is transmitting. This bit gets reset at the end of the last frame (end of last Stop bit).
TBUF is a read/write register.
The RSFT and RBUF registers double-buffer data being received. The USART receiver continually monitors the
signal on the RDX pin for a low level to detect the beginning of a Start bit. Upon sensing this low level, it waits for
half a bit time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and
the remaining bits in the character frame are each sampled a single time, at the mid-bit position. Serial data input
on the RDX pin is shifted into the RSFT register. Upon receiving the complete character, the contents of the
RSFT register are copied into the RBUF register and the Received Buffer Full Flag (RBFL) is set. RBFL is
automatically reset when software reads the character from the RBUF register. RBUF is a read only register.
There is also the RCVG bit which is set high when a framing error occurs and goes low once RDX goes high.
TBMT, XMTG, RBFL and RCVG are read only bits.
SYNCHRONOUS MODE
In this mode data is transferred synchronously with the clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.
This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the USART is the same
as the baud rate.
When an external clock input is selected at the CKX pin, data transmit and receive are performed synchronously
with this clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin as clock output, the device generates the synchronous
clock output at the CKX pin. The internal baud rate generator is used to produce the synchronous clock. Data
transmit and receive are performed synchronously with this clock.
FRAMING FORMATS
The USART supports several serial framing formats (Figure 31). The format is selected using control bits in the
ENU, ENUR and ENUI registers.
The first format (1, 1a, 1b, 1c) for data transmission (CHL0 = 1, CHL1 = 0) consists of Start bit, seven Data bits
(excluding parity) and 7/8, one or two Stop bits. In applications using parity, the parity bit is generated and
verified by hardware.
The second format (CHL0 = 0, CHL1 = 0) consists of one Start bit, eight Data bits (excluding parity) and 7/8, one
or two Stop bits. Parity bit is generated and verified by hardware.
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