COP8SGE5_14 Datasheet, PDF (21/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

www.ti.com
The following occurs upon initialization:
Port L: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
T2CNTRL: CLEARED
T3CNTRL: CLEARED
Accumulator, Timer 1, Timer 2 and Timer 3:
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
Initialized to RAM address 06F Hex
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
S Register: CLEARED
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
USART:
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
COMPARATORS:
CMPSL; CLEARED
WATCHDOG (if enabled):
COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
Copyright © 2000–2013, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7