COP8SGE5_14 Datasheet, PDF (32/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
On wakeup from G7 or Port L, the devices resume execution from the HALT point. On wakeup from RESET
execution will resume from location PC=0 and all RESET conditions apply.
If a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the
chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach
full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the
oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup
signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with
the t_C instruction cycle clock. The t_C clock is derived by dividing the oscillator clock down by a factor of 9. The
Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not
part of the oscillator closed loop. The start-up time-out from the IDLE timer enables the clock signals to be routed
to the rest of the chip.
If an R/C clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as
configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is
set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset.
Each device has two options associated with the HALT mode. The first option enables the HALT mode feature,
while the second option disables the HALT mode selected through bit 0 of the ECON register. With the HALT
mode enable option, the device will enter and exit the HALT mode as described above. With the HALT disable
option, the device cannot be placed in the HALT mode (writing a “1” to the HALT flag will have no effect, the
HALT flag will remain “0”).
The WATCHDOG detector circuit is inhibited during the HALT mode. However, the clock monitor circuit if
enabled remains active during HALT mode in order to ensure a clock monitor error if the device inadvertently
enters the HALT mode as a result of a runaway program or power glitch.
If the device is placed in the HALT mode, with the R/C oscillator selected, the clock input pin (CKI) is forced to a
logic high internally. With the crystal or external oscillator the CKI pin is TRI-STATE.
It is recommended that the user not halt the device by merely stopping the clock in external oscillator mode. If
this method is used, there is a possibility of greater than specified HALT current.
If the user wishes to stop an external clock, it is recommended that the CPU be halted by setting the Halt flag
first and the clock be stopped only after the CPU has halted.
Figure 27. Wakeup from HALT
IDLE MODE
The device is placed in the IDLE mode by writing a “1” to the IDLE flag (G6 data bit). In this mode, all activities,
except the associated on-board oscillator circuitry and the IDLE Timer T0, are stopped.
As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input
Wakeup from the L Port. Alternately, the microcontroller resumes normal operation from the IDLE mode when
the twelfth bit (representing 4.096 ms at internal clock frequency of 10 MHz, t_C = 1 μs) of the IDLE Timer toggles.
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