COP8SGE5_14 Datasheet, PDF (45/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
Figure 34. Interrupt Block Diagram
MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit
and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt
enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All
of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be
controlled by the software.
A maskable interrupt condition triggers an interrupt under the following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is completed.)
An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If different
maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and
the other pending interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable interrupt
condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual
enable bit. When enabling an interrupt, the user should consider whether or not a previously activated (set)
pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous occurrences of the
interrupt should be ignored, the associated pending bit must be reset to zero prior to enabling the interrupt.
Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it will immediately trigger an
interrupt. A maskable interrupt is active if its associated enable and pending bits are set.
An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any interrupt
which occurs during the execution of an instruction is not acknowledged until the start of the next normally
executed instruction is to be skipped, the skip is performed before the pending interrupt is acknowledged.
At the start of interrupt acknowledgment, the following actions occur:
1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting
the current service routine. This feature prevents one maskable interrupt from interrupting another one being
serviced.
2. The address of the instruction about to be executed is pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location.
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