COP8SGE5_14 Datasheet, PDF (54/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
DETECTION OF ILLEGAL CONDITIONS
The device can detect various illegal conditions resulting from coding errors, transient noise, power supply
voltage drops, runaway programs, etc.
Reading of undefined ROM gets zeroes. The opcode for software interrupt is 00. If the program fetches
instructions from undefined ROM, this will force a software interrupt, thus signaling that an illegal condition has
occurred.
The subroutine stack grows down for each call (jump to subroutine), interrupt, or PUSH, and grows up for each
return or POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if there are
more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM).
Undefined RAM from addresses 070 to 07F (Segment 0), and all other segments (i.e., Segments 4 … etc.) is
read as all 1's, which in turn will cause the program to return to address 7FFF Hex. It is recommended that the
user either leave this location unprogrammed or place an INTR instruction (all 0's) in this location to generate a
software interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM.
2. Over “POP”ing the stack by having more returns than calls.
When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure
before restarting (this recovery program is probably similar to that following reset, but might not contain the same
program initialization procedures). The recovery program should reset the software interrupt pending bit using the
RPND instruction.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial SPI compatible synchronous communications interface. The MICROWIRE/PLUS
capability enables the device to interface with MICROWIRE/PLUS or SPI peripherals (i.e. A/D converters, display
drivers, EEPROMs etc.) and with other microcontrollers which support the MICROWIRE/PLUS or SPI interface. It
consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift
clock (SK). Figure 37 shows a block diagram of the MICROWIRE/PLUS logic.
The shift clock can be selected from either an internal source or an external source. Operating the
MICROWIRE/PLUS arrangement with the internal clock source is called the Master mode of operation. Similarly,
operating the MICROWIRE/PLUS arrangement with an external shift clock is called the Slave mode of operation.
The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the
MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock rate is
selected by the two bits, SL0 and SL1, in the CNTRL register. Table 11 details the different clock rates that may
be selected.
Table 11. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
0
0
0
1
1
x
SK Period⁽¹⁾
2 × t_C
4 × t_C
8 × t_C
(1) Where t_C is the instruction cycle clock
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to
shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device may enter the
MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 37 shows how two microcontroller devices
and several peripherals may be interconnected using the MICROWIRE/PLUS arrangements.
54
Submit Documentation Feedback
Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8SGE5 COP8SGE7 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGR7