COP8SGE5_14 Datasheet, PDF (43/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
Effect of HALT/IDLE
The USART logic is reinitialized when either the HALT or IDLE modes are entered. This reinitialization sets the
TBMT flag and resets all read only bits in the USART control and status registers. Read/Write bits remain
unchanged. The Transmit Buffer (TBUF) is not affected, but the Transmit Shift register (TSFT) bits are set to
one. The receiver registers RBUF and RSFT are not affected.
The device will exit from the HALT/IDLE modes when the Start bit of a character is detected at the RDX (L3) pin.
This feature is obtained by using the Multi-Input Wakeup scheme provided on the device.
Before entering the HALT or IDLE modes the user program must select the Wakeup source to be on the RDX
pin. This selection is done by setting bit 3 of WKEN (Wakeup Enable) register. The Wakeup trigger condition is
then selected to be high to low transition. This is done via the WKEDG register (Bit 3 is one.)
If the device is halted and crystal oscillator is used, the Wakeup signal will not start the chip running immediately
because of the finite start up time requirement of the crystal oscillator. The idle timer (T0) generates a fixed (256
t_c) delay to ensure that the oscillator has indeed stabilized before allowing the device to execute code. The user
has to consider this delay when data transfer is expected immediately after exiting the HALT mode.
Diagnostic
Bits CHARL0 and CHARL1 in the ENU register provide a loopback feature for diagnostic testing of the USART.
When these bits are set to one, the following occur: The receiver input pin (RDX) is internally connected to the
transmitter output pin (TDX); the output of the Transmitter Shift Register is “looped back” into the Receive Shift
Register input. In this mode, data that is transmitted is immediately received. This feature allows the processor to
verify the transmit and receive data paths of the USART.
Note that the framing format for this mode is the nine bit format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.
Attention Mode
The USART Receiver section supports an alternate mode of operation, referred to as ATTENTION Mode. This
mode of operation is selected by the ATTN bit in the ENUR register. The data format for transmission must also
be selected as having nine Data bits and either 7/8, one or two Stop bits.
The ATTENTION mode of operation is intended for use in networking the device with other processors. Typically
in such environments the messages consists of device addresses, indicating which of several destinations should
receive them, and the actual data. This Mode supports a scheme in which addresses are flagged by having the
ninth bit of the data field set to a 1. If the ninth bit is reset to a zero the byte is a Data byte.
While in ATTENTION mode, the USART monitors the communication flow, but ignores all characters until an
address character is received. Upon receiving an address character, the USART signals that the character is
ready by setting the RBFL flag, which in turn interrupts the processor if USART Receiver interrupts are enabled.
The ATTN bit is also cleared automatically at this point, so that data characters as well as address characters
are recognized. Software examines the contents of the RBUF and responds by deciding either to accept the
subsequent data stream (by leaving the ATTN bit reset) or to wait until the next address character is seen (by
setting the ATTN bit again).
Operation of the USART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be
transmitted is programmed by setting XBIT9 appropriately. The value of the ninth bit received is obtained by
reading RBIT9. Since this bit is located in ENUR register where the error flags reside, a bit operation on it will
reset the error flags.
Comparators
The device contains two differential comparators, each with a pair of inputs (positive and negative) and an
output. Ports F1–F3 and F4–F6 are used for the comparators. The following is the Port F assignment:
F6 Comparator2 output
F5 Comparator2 positive input
F4 Comparator2 negative input
F3 Comparator1 output
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