COP8SGE5_14 Datasheet, PDF (52/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register
allow the user to pick an upper limit of the service window.
Table 9 shows the four possible combinations of lower and upper limits for the WATCHDOG service window.
This flexibility in choosing the WATCHDOG service window prevents any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit
0 of the WDSVR Register is the Clock Monitor Select bit.
WDSVR
Bit 7
0
0
1
1
x
x
Table 9. WATCHDOG Service Window Select
WDSVR
Bit 6
0
1
0
1
x
x
Clock
Monitor
x
x
x
x
0
1
Service Window
(Lower-Upper Limits)
2048–8k t_C Cycles
2048–16k t_C Cycles
2048–32k t_C Cycles
2048–64k t_C Cycles
Clock Monitor Disabled
Clock Monitor Enabled
CLOCK MONITOR
The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is
ensured not to reject the clock if the instruction cycle clock (1/t_C) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the ECON register. When this ECON bit is 0, the WATCHDOG is
enabled and pin G1 becomes the WATCHDOG output with a weak pullup.
The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the
WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the Clock
Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after coming out of
reset, if the instruction cycle clock frequency has not reached a minimum specified value, including the case
where the oscillator fails to start.
The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR
Register) must match to be a valid write. This write to the WDSVR register involves two irrevocable choices: (i)
the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor. Hence, the first
write to WDSVR Register involves selecting or deselecting the Clock Monitor, select the WATCHDOG service
window and match the WATCHDOG key data. Subsequent writes to the WDSVR register will compare the value
being written by the user to the WATCHDOG service window value and the key data (bits 7 through 1) in the
WDSVR Register. Table 10 shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every lower limit of the service window.
The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is
active low and must be externally connected to the RESET pin or to some other external logic which handles
WATCHDOG event. The WDOUT pin has a weak pullup in the inactive state. This pull-up is sufficient to serve as
the connection to V_CC for systems which use the internal Power On Reset. Upon triggering the WATCHDOG, the
logic will pull the WDOUT (G1) pin low for an additional 16 t_C–32 t_C cycles after the signal level on WDOUT pin
goes below the lower Schmitt trigger threshold. After this delay, the device will stop forcing the WDOUT output
low. The WATCHDOG service window will restart when the WDOUT pin goes high.
A WATCHDOG service while the WDOUT signal is active will be ignored. The state of the WDOUT pin is not
ensured on reset, but if it powers up low then the WATCHDOG will time out and WDOUT will go high.
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