COP8SGE5_14 Datasheet, PDF (53/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error will
continue until the clock frequency has reached the minimum specified value, after which the G1 output will go
high following 16 t_C–32 t_C clock cycles. The Clock Monitor generates a continual Clock Monitor error if the
oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the Clock Monitor
is as follows:
1/t_C > 10 kHz—No clock rejection.
1/t_C < 10 Hz—Ensured clock rejection.
Key
Data
Match
Don't Care
Mismatch
Don't Care
Table 10. WATCHDOG Service Actions
Window
Data
Match
Mismatch
Don't Care
Don't Care
Clock
Monitor
Match
Don't Care
Don't Care
Mismatch
Action
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET.
• Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having
the maximum service window selected.
• The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
• The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR
in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG
errors.
• The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read as key data value of all 0's.
• The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes.
• The CLOCK MONITOR detector circuit is active during both the HALT and IDLE modes. Consequently, the
device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by the program).
• With the single-pin R/C oscillator option selected and the CLKDLY bit reset, the WATCHDOG service window
will resume following HALT mode from where it left off before entering the HALT mode.
• With the crystal oscillator option selected, or with the single-pin R/C oscillator option selected and the
CLKDLY bit set, the WATCHDOG service window will be set to its selected value from WDSVR following
HALT. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following
HALT, but must be serviced within the selected window to avoid a WATCHDOG error.
• The IDLE timer T0 is not initialized with external RESET.
• The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the
T0PND flag. The T0PND flag is set whenever the twelfth bit of the IDLE counter toggles (every 4096
instruction cycles). The user is responsible for resetting the T0PND flag.
• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the
WATCHDOG should not be serviced for at least 2048 instruction cycles following IDLE, but must be serviced
within the selected window to avoid a WATCHDOG error.
• Following RESET, the initial WATCHDOG service (where the service window and the CLOCK MONITOR
enable/disable must be selected) may be programmed anywhere within the maximum service window (65,536
instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within
the initial 2048 instruction cycles without causing a WATCHDOG error.
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