COP8SGE5_14 Datasheet, PDF (69/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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Table 14. OPCODE TABLE⁽¹⁾
F
JP−15
JP−14
JP−13
JP−12
JP−11
JP−10
JP−9
JP−8
JP−7
JP−6
JP−5
JP−4
JP−3
JP−2
JP−1
JP−0
E
JP−31
JP−30
JP−29
JP−28
JP−27
JP−26
JP−25
JP−24
JP−23
JP−22
JP−21
JP−20
JP−19
JP−18
JP−17
JP−16
D
LD 0F0, #i
LD 0F1, #i
LD 0F2, #i
LD 0F3, #i
LD 0F4, #i
LD 0F5, #i
LD 0F6, #i
LD 0F7, #i
LD 0F8, #i
LD 0F9, #i
LD 0FA, #i
LD 0FB, #i
LD 0FC, #i
LD 0FD, #i
LD 0FE, #i
LD 0FF, #i
C
DRSZ 0F0
DRSZ 0F1
DRSZ 0F2
DRSZ 0F3
DRSZ 0F4
DRSZ 0F5
DRSZ 0F6
DRSZ 0F7
DRSZ 0F8
DRSZ 0F9
DRSZ 0FA
DRSZ 0FB
DRSZ 0FC
DRSZ 0FD
DRSZ 0FE
DRSZ 0FF
B
RRCA
A
9
8
RC ADC A,#i ADC A,[B]
*
X A,[X+]
X A,[X−]
VIS
SC
X
A,[B+]
X
A,[B−]
LAID
SUBC A,
#i
SUBC
A,[B]
IFEQ A,#i
IFEQ
A,[B]
IFGT A,#i
IFGT
A,[B]
ADD A,#i ADD A,[B]
RPND
JID AND A,#i AND A,[B]
X A,[X] X A,[B] XOR A,#i XOR A,[B]
*
*
OR A,#i OR A,[B]
NOP
RLCA LD A,#i
IFC
IFNE
A,[B]
LD A,[X+]
LD A,[X−]
LD Md,#i
IFEQ
Md,#i
LD
A,[B+]
LD
A,[B−]
JMPL
IFNE A,#i
LD [B+],#i
LD [B−],#i
X A,Md
IFNC
INCA
DECA
POPA
DIR
JSRL LD A,Md RETSK
LD A,[X]
*
LD
A,[B]
*
LD [B],#i
LD B,#i
RET
RETI
Upper Nibble
7
6
5
IFBIT ANDSZ A, LD B,#0F
0,[B]
#i
IFBIT
1,[B]
*
LD B,#0E
IFBIT
2,[B]
*
LD B,#0D
IFBIT
3,[B]
*
LD B,#0C
IFBIT
4,[B]
CLRA LD B,#0B
IFBIT
5,[B]
SWAPA LD B,#0A
IFBIT
6,[B]
DCORA LD B,#09
IFBIT
7,[B]
PUSHA LD B,#08
SBIT RBIT 0,[B] LD B,#07
0,[B]
SBIT RBIT 1,[B] LD B,#06
1,[B]
SBIT RBIT 2,[B] LD B,#05
2,[B]
SBIT RBIT 3,[B] LD B,#04
3,[B]
SBIT RBIT 4,[B] LD B,#03
4,[B]
SBIT RBIT 5,[B] LD B,#02
5,[B]
SBIT RBIT 6,[B] LD B,#01
6,[B]
SBIT RBIT 7,[B] LD B,#00
7,[B]
(1) Where, i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A
4
IFBNE 0
IFBNE 1
IFBNE 2
IFBNE 3
IFBNE 4
IFBNE 5
IFBNE 6
IFBNE 7
IFBNE 8
IFBNE 9
IFBNE 0A
IFBNE 0B
IFBNE 0C
IFBNE 0D
IFBNE 0E
IFBNE 0F
COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
3
JSR x000–x0FF
JSR x100–x1FF
JSR x200–x2FF
JSR x300–x3FF
JSR x400–x4FF
JSR x500–x5FF
JSR x600–x6FF
JSR x700–x7FF
JSR x800–x8FF
JSR x900–x9FF
JSR xA00–xAFF
JSR xB00–xBFF
JSR xC00–xCFF
JSR xD00–xDFF
JSR xE00–xEFF
JSR xF00–xFFF
2
JMP x000–x0FF
JMP x100–x1FF
JMP x200–x2FF
JMP x300–x3FF
JMP x400–x4FF
JMP x500–x5FF
JMP x600–x6FF
JMP x700–x7FF
JMP x800–x8FF
JMP x900–x9FF
JMP xA00–xAFF
JMP xB00–xBFF
JMP xC00–xCFF
JMP xD00–xDFF
JMP xE00–xEFF
JMP xF00–xFFF
1
0
JP+17 INTR 0
JP+18 JP+2 1
JP+19 JP+3 2
JP+20 JP+4 3
JP+21 JP+5 4
JP+22 JP+6 5
JP+23 JP+7 6
JP+24 JP+8 7
JP+25 JP+9 8
JP+26 JP+10 9
JP+27 JP+11 A
JP+28 JP+12 B
JP+29 JP+13 C
JP+30 JP+14 D
JP+31 JP+15 E
JP+32 JP+16 F
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