COP8SGE5_14 Datasheet, PDF (8/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
DC Electrical Characteristics (continued)
−40°C ≤ T_A ≤ +85°C unless otherwise specified.
Parameter
IDLE Current⁽²⁾
Conditions
CKI = 15 MHz
CKI = 10 MHz
CKI = 4 MHz
Input Levels (V_IH, V_IL)
RESET
V_CC = 5.5V, t_C = 0.67 μs
V_CC = 5.5V, t_C = 1 μs
V_CC = 4.5V, t_C = 2.5 μs
Logic High
Logic Low
CKI, All Other Inputs
Logic High
Logic Low
Internal Bias Resistor for the
Crystal/Resonator Oscillator
CKI Resistance to V_CC or GND when R/C
Oscillator is selected
V_CC = 5.5V
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis
Output Current Levels
V_CC = 5.5V
V_CC = 5.5V, V_IN = 0V
V_CC = 5.5V
D Outputs
Source
Sink
All Others
V_CC = 4.5V, V_OH = 3.3V
V_CC = 2.7V, V_OH = 1.8V
V_CC = 4.5V, V_OL = 1.0V
V_CC = 2.7V, V_OL = 0.4V
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink Current per Pin⁽⁴⁾
V_CC = 4.5V, V_OH = 2.7V
V_CC = 2.7V, V_OH = 1.8V
V_CC = 4.5V, V_OH = 3.3V
V_CC = 2.7V, V_OH = 1.8V
V_CC = 4.5V, V_OL = 0.4V
V_CC = 2.7V, V_OL = 0.4V
V_CC = 5.5V
D Outputs and L0 to L3
All Others
Maximum Input Current without Latchup⁽⁵⁾
Room Temp.
RAM Retention Voltage, Vr
V_CC Rise Time from a V_CC ≥ 2.0V
EPROM Data Retenton⁽⁷⁾,⁽⁴⁾
Input Capacitance
Load Capacitance on D2
See ⁽⁶⁾
T_A = 55°C
See ⁽⁴⁾
See ⁽⁴⁾
Min
Typ
Max
Units
2.25
mA
1.5
mA
0.8
mA
0.8 V_cc
0.7 V_cc
0.5
1
5
8
−2
−40
0.25 V_cc
V
0.2 V_cc
V
V
0.2 V_cc
V
2
MΩ
11
kΩ
+2
μA
−250
μA
V
−0.4
-0.2
10
2
−10.0
-2.5
−0.4
-0.2
1.6
0.7
−2
2.0
12
>29
mA
mA
mA
mA
−110
μA
-33
μA
mA
mA
mA
mA
+2
μA
15
3
±200
7
1000
mA
mA
mA
V
μs
years
pF
pF
(4) Parameter characterized but not tested.
(5) Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > V_CC and the pins will have sink
current to V_CC when biased at voltages > V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective
resistance to V_CC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING:
Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
(6) Rise times faster than the minimum specification may trigger an internal power-on-reset.
(7) TI uses the High Temperature Storage Life (HTSL) test to evaluate the data retention capabilities of the EPROM memory cells used in
our OTP microcontrollers. Qualification devices have been stressed at 150°C for 1000 hours. Under these conditions, our EPROM cells
exhibit data retention capabilities in excess of 29 years. This is based on an activation energy of 0.7eV derated to 55°C.
8
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