COP8SGE5_14 Datasheet, PDF (22/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with
the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor
circuits are inhibited during reset. The WATCHDOG service window bits being initialized high default to the
maximum WATCHDOG service window of 64k t_C clock cycles. The Clock Monitor bit being initialized high will
cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the
termination of reset. A Clock Monitor error will cause an active low error output on pin G1. This error output will
continue until 16 t_C–32 t_C clock cycles following the clock frequency reaching the minimum specified value, at
which time the G1 output will go high.
External Reset
The RESET input when pulled low initializes the device. The RESET pin must be held low for a minimum of one
instruction cycle to ensure a valid reset. During Power-Up initialization, the user must ensure that the RESET pin
is held low until the device is within the specified V_CC voltage. An R/C circuit on the RESET pin with a delay 5
times (5x) greater than the power supply rise time or 15 μs whichever is greater, is recommended. Reset should
also be wide enough to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT mode.
A recommended reset circuit for this device is shown in Figure 18.
RC >5x power supply rise time or 15 μs, whichever is greater.
Figure 18. Reset Circuit Using External Reset
On-Chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON register. When enabled, the device generates an
internal reset as V_CC rises to a voltage level above 2.0V. The on-chip reset circuitry is able to detect both fast
and slow rise times on V_CC (V_CC rise time between 10 ns and 50 ms).To ensure an on-chip power-on-reset,
V_CCmust start at a voltage less than the start voltage specified in the DC characteristics. Also, if V_CC be lowered
to the start voltage before powering back up to the operating range. If this is not possible, it is recommended that
external reset be used.
Under no circumstances should the RESET pin be allowed to float. If the on-chip Power-On Reset feature is
being used, RESET pin should be connected directly, or through a pull-up resistor, to V_CC. The output of the
power-on reset detector will always preset the Idle timer to 0FFF(4096 t_C). At this time, the internal reset will be
generated.
If the Power-On Reset feature is enabled, the internal reset will not be turned off until the Idle timer underflows.
The internal reset will perform the same functions as external reset. The user is responsible for ensuring that V_CC
is at the minimum level for the operating frequency within the 4096 t_C. After the underflow, the logic is designed
such that no additional internal resets occur as long as V_CC remains above 2.0V.
The contents of data registers and RAM are unknown following the on-chip reset.
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