COP8SGE5_14 Datasheet, PDF (10/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings⁽¹⁾⁽²⁾
Supply Voltage (V_CC)
Voltage at Any Pin
Total Current into V_CC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
ESD Protection Level
7V
−0.3V to V_CC +0.3V
100 mA
110 mA
−65°C to +140°C
2kV (Human Body Model)
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not
ensured when operating the device at absolute maximum ratings.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
DC Electrical Characteristics
−40°C ≤ T_A ≤ +125°C unless otherwise specified.
Parameter
Conditions
Operating Voltage
Power Supply Rise Time
V_CC Start Voltage to Ensure POR
Power Supply Ripple⁽¹⁾
Supply Current⁽²⁾
Peak-to-Peak
CKI = 10 MHz
CKI = 4 MHz
HALT Current⁽³⁾
IDLE Current⁽²⁾
V_CC = 5.5V, t_C = 1 μs
V_CC = 4.5V, t_C = 2.5 μs
V_CC = 5.5V, CKI = 0 MHz
CKI = 10 MHz
CKI = 4 MHz
Input Levels (V_IH, V_IL)
RESET
V_CC = 5.5V, t_C = 1 μs
V_CC = 4.5V, t_C = 2.5 μs
Logic High
Logic Low
CKI, All Other Inputs
Logic High
Logic Low
Internal Bias Resistor for the
Crystal/Resonator Oscillator
CKI Resistance to V_CC or GND when R/C
Oscillator is selected
V_CC = 5.5V
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis
V_CC = 5.5V
V_CC = 5.5V, V_IN = 0V
V_CC = 5.5V
Min
Typ
Max
Units
4.5
5.5
V
10
50 x 10⁶ ns
0
0.25
V
0.1 V_cc
V
6.0
mA
2.1
mA
<4
10
μA
1.5
mA
0.8
mA
0.8 V_cc
0.7 V_cc
0.5
V
0.2 V_cc
V
V
0.2 V_cc
V
1
2
MΩ
5
8
11
kΩ
−5
−35
0.25 V_cc
+5
μA
−400
μA
V
(1) Maximum rate of voltage change must be < 0.5 V/ms.
(2) Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, External Oscillator, inputs connected to V_CC and
outputs driven low but not connected to a load.
(3) The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high
internally. In the crystal or external configuration, CKI is TRI-STATE. Measurement of I_DD HALT is done with device neither sourcing nor
sinking current; with L. F, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not
driving a load; all inputs tied to V_CC; clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data
register.
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